India to Scale Chip Design Base, Targets 50 Fabless Firms in Next Phase

India is looking to significantly expand its domestic semiconductor design ecosystem, with the government setting a target to support at least 50 fabless chip firms in the next phase of its Design Linked Incentive (DLI) program, as it seeks to reduce import dependence and build a more resilient electronics supply chain.

The push builds on early outcomes from the DLI scheme under the Semicon India program, which was launched in 2022 to encourage indigenous chip design rather than focus solely on fabrication. 

Union Minister for Electronics and Information Technology Ashwini Vaishnaw said the government’s approach reflects a long-term strategy aimed at developing the full semiconductor value chain.

“The program was conceived in 2022 with a clear vision to build the entire semiconductor ecosystem and pursue a long-term strategy rather than isolated schemes,” Vaishnaw said, adding that the effort was aimed at helping India move from a services-led economy to a product-driven one.

The current phase of the DLI scheme supports 24 startups working on chip designs across areas including system-on-chips, telecom and wireless technologies, power management, artificial intelligence and internet-of-things applications. 

According to government data, several of these firms have already completed tape-outs and begun validating products with customers.

“Many startups have already completed tape-outs, validated products and found market traction,” Vaishnaw said, arguing that easing access to electronic design automation tools, intellectual property libraries and fabrication support has helped lower entry barriers for first-time chip designers.

The numbers underscore the scale of activity the government is trying to seed. Companies and academic institutions under the program have collectively logged about 22.5 million hours on advanced EDA tools. 

Around 67,000 students and more than 1,000 startup engineers have participated. Academic institutions have completed 122 tape-outs, with 56 chips fabricated at the Semiconductor Laboratory in Mohali. Startups have completed 16 tape-outs so far, including six chips produced at advanced nodes such as 12 nanometres.

The minister said the government now plans to scale up support. He expressed confidence that India would see globally competitive fabless companies emerge in the coming years. 

He also noted that startups under the scheme have attracted close to ₹430 crore in venture capital funding, with 14 of the 24 supported firms securing external investment.

Vaishnaw said international perception of India’s semiconductor push has shifted in recent years. Referring to discussions at the World Economic Forum in Davos, he said global industry leaders now recognize the scale and seriousness of India’s plans and are keen to explore partnerships.

As part of the next phase, the government has identified six priority design areas: compute systems, radio frequency and wireless technologies, networking, power management, sensors and memory.

Vaishnaw said these form the backbone of modern electronic systems used in sectors ranging from defence and space to automotive and railways.

On manufacturing, he said the existing facility at Mohali will continue to support 180 nanometre tape-outs, while the upcoming fabrication unit at Dholera will enable production up to 28 nanometres. Over the longer term, he said India aims to develop capabilities at 3 nanometre and 2 nanometre nodes under the proposed Semicon 2.0 phase.

Vaishnaw said India could be in a position to design and manufacture chips for about 70 to 75% of domestic needs by 2029. By 2035, he said, the country aims to be among the leading semiconductor nations globally.

The minister also announced that the government will institute Deep Tech Awards in 2026 to recognise innovation across areas including semiconductors, artificial intelligence, biotechnology and space. The first set of awards is expected towards the end of the year.