 
        
        Policy 50
V. Narayanan
Secretary, Department of Space; Chairman, Indian Space Research Organisation
 
        
        Secretary, Department of Space; Chairman, Indian Space Research Organisation
 
        
        Fabricated on a 180-nanometer CMOS line, the device has already been tested in space aboard the PSLV-C60 mission earlier this year, proving its resilience for launch and orbital conditions.
